M.Tech.(DSCE)
II Semester
DESIGN OF FAULT TOLERANT SYSTEMS
UNIT I
BASIC CONCEPTS: Reliability concepts, Failure & Faults, Reliability and failure rate, Relation between reliability and Mean time between failure, Maintainability and Availability, Reliability of series, Parallel and Parallel-Series combinational circuits.
UNIT II
FAULT TOLERANT DESIGN: Basic concepts – Static, dynamic, hybrid, Triple Modular Redundant System, Self purging redundancy, Siftout redundancy (SMR), SMR Configuration, Use of error correcting code, Time redundancy and software redundancy.
UNIT III
SELF CHECKING CIRCUITS: Basic concepts of Self checking circuits, Design of Totally Self Checking checker, Checkers using m out of n codes, Berger code, Low cost residue code.
UNIT IV
FAIL SAFE DESIGN: Strongly fault secure circuits, fail safe design of sequential circuits using partition theory and Berger code, Totally self checking PLA design.
UNIT V
DESIGN FOR TESTABILITY FOR COMBINATIONAL CIRCUITS: Basic concepts of testability, controllability and observability, the Reed Muller’s expansion technique, OR-AND-OR design, use of control and syndrome testable design.
UNIT VI
Theory and operation of LFSR, LFSR as Signature analyzer, Multiple-input Signature Register.
UNIT VII
DESIGN FOR TESTABILITY FOR SEQUENTIAL CIRCUITS: Controllability and observability by means of scan register, Storage cells for scan design, classic scan design, Level Sensitive Scan Design (LSSD).
UNIT VIII
BUILT IN SELF TEST: BIST concepts, Test pattern generation for BIST exhaustive testing, Pseudorandom testing, pseudo exhaustive testing, constant weight patterns, Generic offline BIST architecture.
TEXT BOOKS:
1. Parag K. Lala – “Fault Tolerant & Fault Testable Hardware Design” (PHI)
2. M. Abramovili, M.A. Breues, A. D. Friedman – “Digital Systems Testing and Testable Design” Jaico publications.
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