VERIFICATION OF LOGIC GATES
AIM:
To develop the source code for logic gates by using VHDL/VERILOG and obtain the simulation, synthesis.
ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
LOGIC DIAGRAM:
AND GATE: OR GATE:
A | B | Y=A+B |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
A | B | Y=AB |
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
NOT GATE: NAND GATE:
A | B | Y=(AB)’ |
0 | 0 | 1 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
A | Y=A’ |
0 | 1 |
1 | 0 |
NOR GATE: XOR GATE:
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE
A | B | Y=(A+B)’ |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 0 |
A | B | |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
XNOR GATE:
LOGIC DIAGRAM: TRUTH TABLE:
A | B | |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
VHDL SOURCE CODE
--Design : VERIFICATION OF LOGIC GATES
--Description : To implement LOGIC GATES
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
AND GATE: (Program)
Entity andgate is
Port (a: in std_logic;
b: in std_logic;
c: out std_logic);
End andgate;
Architecture Behavioral of andgate is
Begin
c<=a and b;
End Behavioral;
OR GATE: (Program)
Entity orgate is
Port (a: in std_logic;
b: in std_logic;
c: out std_logic);
End orgate;
Architecture Behavioral of orgate is
Begin
c<=a or b;
End Behavioral;
NOT GATE:
Entity notgate is
Port (a: in std_logic;
abar: out std_logic);
End notgate;
Architecture Behavioral of notgate is
Begin
Abar<= not (a);
End Behavioral;
NAND GATE:
Entity nandgate is
Port (a: in std_logic;
b: in std_logic;
c: out std_logic);
End nandgate;
Architecture Behavioral of nandgate is
Begin
c<= a nand b;
End Behavioral;
NOR GATE:
Entity norgate is
Port (a: in std_logic;
b: in std_logic;
c: out std_logic);
End norgate;
Architecture Behavioral of norgate is
Begin
c<=a nor b;
End Behavioral;
XOR GATE:
Entity exorgate is
Port ( a,b : in std_logic;
c : out std_logic);
End exorgate;
Architecture Behavioral of exorgate is
Begin
c<=a xor b;
End Behavioral;
XNOR GATE:
Entity exnorgate is
Port ( a,b : in std_logic;
c : out std_logic);
End exnorgate;
Architecture Behavioral of exnorgate is
Begin
c<=a xnor b;
End Behavioral;
VERILOG CODE:
And Gate:
Module andgate (a, b, c);
Input a, b;
Output c;
Assign c=a & b;
Endmodule
Or Gate:
Module orgate (a, b, c);
Input a, b;
Output c;
Assign c= a |b;
End module
Not Gate:
Module notgate (a, abar);
Input a;
Output abar;
Assign abar = ~a;
Endmodule
Nand gate:
Module nandgate (a, b, c);
Input a, b;
Output c;
Assign c = ~ (a & b);
Endmodule
Nor gate:
Module norgate (a, b, c);
Input a, b;
Output c;
Assign c = ~ (a | b);
Endmodule
X-nor gate:
Module exnorgate(a,b, c);
Input a,b;
Output c;
Assign c = a ^~ b;
Endmodule
X-or -gate:
Module exorgate(a,b, c);
input a,b;
output c;
assign c = a ^ b;
endmodule
TEST BENCH :
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
Entity tgates is
End;
Architecture atgates2 of tgates is
Component gate2 is
Port ( a: in std_logic;
B: in std_logic;
C: out std_logic);
End component;
Signal x, y, z: bit:
Begin
U:gate2 port map(a=>x, b=>y, c=>z);
P1: process
Begin
X<='0'; y<='0'; wait for 50ns;
X<='0'; y<='1'; wait for 50ns;
X<='1'; y<='0'; wait for 50ns;
X<='1'; y<='1'; wait for 50ns;
End process p1;
End atgates2;
Simulation output:
RESULT:
Thus the gates (AND, OR, NOT, NAND, NOR, XOR and XNOR GATES) are simulated and synthesis with VHDL/VERILOG program.
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