JNTU DIGITAL SYSTEMS DESIGN LAB MANUVLAS

M.Tech.(DSCE)                                                                                                       

II Semester

DIGITAL SYSTEMS DESIGN LAB

CYCLE 1:

1. Simulation and Verification of Logic Gates.
2. Design and Simulation of Half adder, Serial Binary Adder, Multi Precession Adder, Carry Look Ahead Adder and Full Adder.
3. Simulation and Verification of Decoder, MUXs, Encoder using all Modeling Styles.
4. Modeling of Flip-Flops with Synchronous and Asynchronous reset.
5. Design and Simulation of Counters- Ring Counter, Johnson Counter, and Up- Down Counter, Ripple Counter.
6. Design of a N- bit Register of Serial-in Serial-out, Serial in Parallel out, Parallel in Serial out and Parallel in Parallel Out.
7. Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
8. 4- Bit Multiplier, Divider. (for 4-Bit Operand)
9. Design ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s COMPLIMENT, Multiplication, Division.

CYCLE 2: After completing cycle 1, Digital Circuit Description Using Verilog/ VHDL.

1. Verification of the Functionality of the circuit using function Simulators.
2. Timing Simulator for Critical Path time Calculation.
3. Synthesis of Digital Circuit.
4. Place and Router Techniques for FPGA’s like Xilinx, Altera, Cypress, etc.,
5. Implementation of Design using FPGA and CPLD Devices.