| Digital Computers and Information: - Βinary signals, information representation, generic computer architecture - Number systems, operations and conversions: decimal, binary, octal, hex. - Codes: BCD, parity, Gray, ASCII, Unicode | Chapter 1, Unicode Supplement, EDC Supplement |
| Combinational Logic: - Binary logic/gates - Boolean Algebra, functions, properties and theorems - Standard forms: minterms/maxterms, SoP, PoS Karnaugh maps: 2, 3, and 4 variables maps - Quine-McCluskey Boolean function minimization - Two-level/Multilevel circuit optimization |
| Basic Logic Gates, popular technologies: - NAND/NOR gates and circuits: two-level and multi-level implementations - Exclusive-OR gates: odd function, parity function - High impedance outputs: tri-state buffers and transmission gates - Integrated circuits: levels of integration, digital logic families, negative/positive logic - CMOS circuits: switch models, nets of switches, fully complementary CMOS, basic gates, complex gates, transmission gate | Chapter 2, 3.3, 6.1-6.2 CMOS Supplement& Notes |
| Combinational Logic Design: - Design principles (hierarchy, top-down design, CAD, HDLs, logic synthesis) - Combinational circuit analysis and timing - Design procedure (examples) - Technology mapping |
| Combinational Functions and Circuits: - Decoders, expansion, circuit implementation using decoders - Encoders, expansion, priority encoders - Multiplexers, implementation, Quad-MUX, MUX as universal gate - Circuit implementation using MUXes - Iterative Combinational Circuits - Binary Adders (HA, FA, ripple-carry, carry-lookahead) - Binary Subtraction (unsigned, 1's and 2's complements) - Binary Adder/Subtractors - Binary Adder/Subtractors (signed numbers) - Binary Multiplication - Other Arithmetic functions - VHDL Language for Combinational Circuit Design - Circuit implementation using PLDs (ROM, PLA, PAL) | Chapter 3, 4, 6.8, VHDLa Supplement, VHDLb Supplement, PLDs Notes, CLA Supplement, Dec_Arith, Supplement, Mult_Div Supplement |
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