| Introduction & Outline | 13, | |
| Process and Tools Overview | 15, | |
| Magic Layout Intro, Elementary Gates | 20, | |
| Heirarchy; Simulation Intro | 22, | |
| Adders, Layout Techniques | 27, | |
| Control Structures; Sequential Machines | 29, | |
| All About MOSFETS | 3, | |
| FET Parasitics | 10, | |
| Fet Characteristics -> Circuit Behavior | 12, | |
| Tau Model, Buffer Chains | 17, | |
| IRSIM techniques | 24, | |
| Power, Margins, Noise | 26, | |
| Other Logic Styles | 3, | |
| Clocking | 17, | |
| The SECS electrical rule checker | 17, | |
| Latches | 19, | |
| Flip Flops, Failure Mechanisms | 24, | |
| Guest Lecture: Corporate IC Design | 26, | |
| Memory Cells | 31, | |
| More on SRAMs | 2, | |
| The Verilog Hardware Description Language | 7, | |
| Analog CMOS | 9, | |
| Adders Revisited | 14, | |
| Guest Lecture: Metastability | 21, | |
| I/O pads, ESD, High Speed Signaling | 23, |
Tuesday, June 21, 2011
FREE VLSI Course Notes for learning at Home
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