binary adders vhdl programe notes

BINARY ADDERS

AIM:
To develop the source code for adders and subtractors by using VHDL/VERILOG and obtain the simulation.

ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis is report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.

LOGIC DIAGRAM:

BASIC ADDERS & SUBTRACTORS:

HALF ADDER:

LOGIC DIAGRAM: TRUTH TABLE:




FULL ADDER: TRUTH TABLE

LOGIC DIAGRAM:





RIPPLE CARRY ADDER:

LOGIC DIAGRAM:


VHDL SOURCE CODE
--Design : ADDERS
--Description : To implement ADDERS
--
HALF ADDER:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity halfadder is
Port ( a,b : in std_logic;
sum,carry : out std_logic);
end halfadder;

DATAFLOW MODEL

architecture Behavioral of halfadder is
begin
sum<= a xor b; carry<= a and b; end Behavioral; STRUCTURAL MODEL architecture structural of haifadd is component and2 port(p:in std_logic; q:in std_logic; r:out std_logic); end component; component xor2 port(p:in std_logic; q:in std_logic; r:out std_logic); end component; begin x1: xor2 port map(a,b,sum); a1: and2 port map(a,b,carry); end structural; BEHAVIORAL MODEL architecture Behavioral of halfadd is begin process(a,b) begin sum<=a xor b; carry<=a and b; end process; end Behavioral; VERILOG CODE: DATAFLOW MODEL module halfadder(a,b, sum,carry); input a,b; output sum,carry; assign sum=a^b; assign carry=a&b; endmodule BEHAVIORAL MODEL module halfadd(a, b, sum, carry); input a; input b; output sum; output carry; reg sum,carry; always @(a or b) begin sum=a^b; carry=a &b; end endmodule TEST BENCH Entity test is End test; Architecture atest of test is Component ha is Port ( a: in std_logic; b: in std_logic; sum,carry: out std_logic); End Component; Signal w,x, y, z: Bit: Begin X1:ha portmap(w,x, y, z); p1: process Begin w<='0'; x<='0'; wait for 50ns; w<='0'; x<='1'; wait for 50ns; w<='1'; x<='0'; wait for 50ns; w<='1'; x<='1'; wait for 50ns; End Process P1; End atest; FULL ADDER: VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder is Port ( a,b,cin : in std_logic; sum,carry : out std_logic); end fulladder; DATAFLOW MODEL architecture Behavioral of fulladder is signal p,q,r,s:std_logic; begin p<= a xor b; sum<= p xor cin; q<= a and b; r<= b and cin; s<= a and cin; carry<=q or r or s; end Behavioral; STRUCTURAL MODEL Architecture struct of fulladd is component and2 port(p:in std_logic; q:in std_logic; r:out std_logic); end component; component xor2 port(p:in std_logic; q:in std_logic; r:out std_logic); end component; component or3 port(p,q,r:in std_logic; s:out std_logic); end component; signal s1,s2,s3,s4:std_logic; Begin x1: xor2 port map(a,b,s4); x2: xor2 port map(c,s4,sum); a1: and2 port map(a,b,s1); a2: and2 port map(a,c,s3); a3: and2 port map(c,b,s2); r1: or3 port map(s1,s2,s3,carry); End struct; BEHAVIORAL MODEL Architecture Behavioral of fulladd is Begin Process(a,b,c) Variable s1,s2,s3,s4:std_logic; Begin S1:=a xor b; Sum<=c xor s1; S2:=a and b; S3:=a and c; S4:=b and c; Carry<=s2 or s3 or s4; End process; End Behavioral; VERILOG CODE: DATAFLOW MODEL module fulladder(a,b,cin, sum,carry); input a,b,cin; output sum,carry; reg sum,carry; reg w,x,y,z; always @ (a or b or cin) begin w=a^b; sum=w^cin; x=a&b; y=b&cin; z=a&cin; carry=x|y|z; end endmodule BEHAVIORAL MODEL Module fulladd(a, b, cin, sum, carry); input a; input b; input cin; output sum,carry; reg sum,carry; always @(a or b or cin) begin sum =((a ^ b) ^ cin); carry =((a & b)|(a & cin)|(b & cin)); end Endmodule TEST BENCH ARCHITECTURE behavior OF tsetFA_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT fulladd PORT( a,b,c : IN std_logic; sum : OUT std_logic; carry : OUT std_logic); END COMPONENT; BEGIN X1: fulladd PORT MAP( a => a,b => b,c => c,sum => sum,carry => carry);
p1 : PROCESS

BEGIN

a<='0';b<='0';c<='0'; wait for 100 ps; a<='0';b<='0';c<='1'; wait for 100 ps; a<='0';b<='1';c<='0'; wait for 100 ps; a<='0';b<='1';c<='1'; wait for 100 ps; a<='1';b<='0';c<='0'; wait for 100 ps; a<='1';b<='0';c<='1'; wait for 100 ps; a<='1';b<='1';c<='0'; wait for 100 ps; a<='1';b<='1';c<='1'; wait for 100 ps; END PROCESS; END; SIMULATION OUTPUT: RIPPLE CARRY ADDER VHDL SOURCE CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rippleadder is Port ( x1,x2,x3,x4,x5,x6,x7,x8 : in std_logic; y1,y2,y3,y4,y5,y6,y7,y8 : in std_logic; cin : in std_logic; carry : out std_logic; sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8 : out std_logic); end rippleadder; architecture structural of rippleadder is component fulladd1 Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end component; signal c1,c2,c3,c4,c5,c6,C7 : std_logic; begin f1 :fulladd1 port map (x1,y1,cin,sum1,c1); f2 :fulladd1 port map (x2,y2,c1,sum2,c2); f3 :fulladd1 port map (x3,y3,c2,sum3,c3); f4 :fulladd1 port map (x4,y4,c3,sum4,C4); f5 :fulladd1 port map (x5,y5,c4,sum5,c5); f6 :fulladd1 port map (x6,y6,c5,sum6,c6); f7 :fulladd1 port map (x7,y7,c6,sum7,c7); f8 :fulladd1 port map (x8,y8,c7,sum8,carry); end structural; verilog source code module ripplecarry(fa1,fb1,fa2,fb2,fa3,fb3,fa4,fb4, fa5,fb5,fa6,fb6,fa7,fb7,fa8,fb8,fcin,fsum1,fsum2,fsum3,fsum4, fsum5,fsum6,fsum7,fsum8,fcarry); input fa1,fb1,fa2,fb2,fa3,fb3,fa4,fb4, fa5,fb5,fa6,fb6,fa7,fb7,fa8,fb8; output fsum1,fsum2,fsum3,fsum4, fsum5,fsum6,fsum7,fsum8; input fcin; output fcarry; wire [1:7]ftemp; fulladder f1(fa1,fb1,fcin, fsum1,ftemp[1]), f2(fa2,fb2,ftemp[1],fsum2,ftemp[2]), f3(fa3,fb3,ftemp[2],fsum3,ftemp[3]), f4(fa4,fb4,ftemp[3],fsum4,ftemp[4]); f5(fa5,fb5,ftemp[4], fsum5,ftemp[5]), f6(fa6,fb6,ftemp[5],fsum6,ftemp[6]), f7(fa7,fb7,ftemp[6],fsum7,ftemp[7]), f8(fa8,fb8,ftemp[7],fsum8,fcarry); endmodule TEST BENCH LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY ripple_vhd IS END ripple_vhd; ARCHITECTURE behavior OF ripple_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT rippleadder PORT( x1 : IN std_logic; x2 : IN std_logic; x3 : IN std_logic; x4 : IN std_logic; x5 : IN std_logic; x6 : IN std_logic; x7 : IN std_logic; x8 : IN std_logic; y1 : IN std_logic; y2 : IN std_logic; y3 : IN std_logic; y4 : IN std_logic; y5 : IN std_logic; y6 : IN std_logic; y7 : IN std_logic; y8 : IN std_logic; cin : IN std_logic; carry : OUT std_logic; sum1 : OUT std_logic; sum2 : OUT std_logic; sum3 : OUT std_logic; sum4 : OUT std_logic; sum5 : OUT std_logic; sum6 : OUT std_logic; sum7 : OUT std_logic; sum8 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL x1 : std_logic := '0'; SIGNAL x2 : std_logic := '0'; SIGNAL x3 : std_logic := '0'; SIGNAL x4 : std_logic := '0'; SIGNAL x5 : std_logic := '0'; SIGNAL x6 : std_logic := '0'; SIGNAL x7 : std_logic := '0'; SIGNAL x8 : std_logic := '0'; SIGNAL y1 : std_logic := '0'; SIGNAL y2 : std_logic := '0'; SIGNAL y3 : std_logic := '0'; SIGNAL y4 : std_logic := '0'; SIGNAL y5 : std_logic := '0'; SIGNAL y6 : std_logic := '0'; SIGNAL y7 : std_logic := '0'; SIGNAL y8 : std_logic := '0'; SIGNAL cin : std_logic := '0'; --Outputs SIGNAL carry : std_logic; SIGNAL sum1 : std_logic; SIGNAL sum2 : std_logic; SIGNAL sum3 : std_logic; SIGNAL sum4 : std_logic; SIGNAL sum5 : std_logic; SIGNAL sum6 : std_logic; SIGNAL sum7 : std_logic; SIGNAL sum8 : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: rippleadder PORT MAP( x1 => x1,
x2 => x2,
x3 => x3,
x4 => x4,
x5 => x5,
x6 => x6,
x7 => x7,
x8 => x8,
y1 => y1,
y2 => y2,
y3 => y3,
y4 => y4,
y5 => y5,
y6 => y6,
y7 => y7,
y8 => y8,
cin => cin,
carry => carry,
sum1 => sum1,
sum2 => sum2,
sum3 => sum3,
sum4 => sum4,
sum5 => sum5,
sum6 => sum6,
sum7 => sum7,
sum8 => sum8);
tb : PROCESS
BEGIN
x1 <= '1';x2 <= '1';x3 <= '0';x4 <= '0';x5 <= '0';x6 <= '1';x7 <= '1';x8 <= '0';
y1<= '0';y2 <= '1';y3 <= '1';y4 <= '0';y5 <= '1';y6 <= '0';y7 <= '1';y8 <= '0';
cin <= '0';
wait for 100 ps;
cin <= '1';
wait for 100 ps;
END PROCESS;
END;


SYNTHESIS OUTPUT RIPPLE ADDER





RESULT:
Thus the outputs of Adders,Subtractors and Fast Addres are verified by simulating the VHDL and VERILOG code.