Saturday, February 26, 2011

Packet Switch Architecture


CS-534: Packet Switch Architecture


  • Bibliography.

  • Course Description [old PDF]

    Lecture Notes, Transparencies, Exercises:

    This Year:

    Chapter 1: Basic Concepts and Queueing Architectures
    Chapter 2: Link and Memory Architectures and Technology
    • 2.1 Links, Throughput/Buffering, Multi-Access Overheads [Slides in PDF] [Slides Handout in PDF]
      [to be done: move "cut-through" from 3.1 to 2.1. Older text for section 2.1.1: [Text in HTML] [Text in PDF] ]
    • Exercises 2 (due 2 March- wk.3.2): Transmission Rate and Throughput, Turn-Around Overhead [HTML] [PDF]


    • 2.2 Memory Technologies: On-chip / Off-chip SRAM, DRAM [Slides in PDF] [Slides Handout in PDF]
    • Exercises 3 (due 6 Mar.- wk.(4) 5.2): Memory Access Rate, Variable-Size-Packet Segmentation [HTML] [old '08 PDF]
    • 2.A Appendix: Elastic Buffers for Cross-Clock Communication [Slides in PDF] [Slides Handout in PDF]

    Chapter 3: Time Switching, Multi-Queue Memories, Shared Buffers, Output Queueing Family
    • 3.1 Time Division Multiplexing (TDM), Time Switching, Cut-Through [Slides in PDF] [Slides Handout in PDF]
    • Exercises 4 (due 9 Mar.- wk.(5) 6.1): Switch Generations, Cut-Through [HTML] [old '08 PDF]
    • 3.2 Wide Memories for High Throughput, Segmentation Overhead [Slides in PDF] [Slides Handout in PDF]
      [animation of the operation of the pipelined memory]
    • 3.3, 3.4 Multiple Queues within a Buffer Memory, Queueing for Multicast Traffic [Slides in PDF] [Slides Handout in PDF]
      [animated PPT for queue operations with free-block preallocation]
    • Exercises 5 (due 13 Mar. - wk.6.2): Linked-List Queue Management [HTML] [old '08 PDF]
    • 3.5 Shared Buffering and the Output Queueing Family [Slides in PDF] [Slides Handout in PDF]
    • Exercises 6 (due 20 Mar.- wk.7.2): Multi-Packet Queue Blocks, Multicast Queues [HTML] [old '08 PDF]

    Chapter 4: Input Queueing (Time-Space Switching) and Combination Architectures
    • 4.1 Introduction: Time-Space Switching, Single-Queue Input Queueing [Slides - PDF] [Slides Handout - PDF]
    • 4.2 Input Queueing with VOQ's: Crossbar Scheduling [Slides - PDF] [Slides Handout - PDF]
    • 4.3 Advanced Topics: Pipelined, Packet-Mode, and Enveloppe Scheduling [Slides - PDF] [Slides Handout - PDF]
    • 4.4, 4.5 Combined Input-Output Queueing (CIOQ), Combined Input-Crosspoint Queueing (CICQ) [Slides - PDF] [Slides Handout - PDF]
    • Exercises 7 (due 30 Mar.- wk.9.1): Input Queueing and Crossbar Scheduling [HTML] [old '08 PDF]
    • Exercises 8 (due 10 Apr.-wk.10.3): Queueing Architectures SRAM Cost [HTML] [old '08 PDF]

    Chapter 5: Switching Fabrics, Inverse Multiplexing
    • [Slides - PDF] [Slides Handout - PDF]:
      • 5.1 Byte Slicing, Inverse Multiplexing (Adaptive/Multipath Routing)
      • 5.2 Scalable, Non-Blocking Switching Fabrics
      • 5.3 What about Scalable Scheduling?
    • Exercises 9 (due 27 Apr.- wk.11.1): TST and Clos Circuit Switch Scheduling [HTML] [old '08 PDF]
    • Exercises 10 (due 6 May - wk.12.2): Switching Fabric Topologies [HTML] [old '08 PDF]

    Chapter 6: Flow Control in Buffered Switching Fabrics
    ACACES 2007 (Third International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems) Slides for the course on "Queue and Flow Control Architectures for Interconnection Switches", by Manolis Katevenis, in PDF:
    1. [Slides] [Handouts] Flow and Congestion Control in Switching Fabrics

    Chapter 7: Output Scheduling for Quality-of-Service (QoS) Guarantees
    Other Topics: Please refer to the bibliography pointed below (2003 and older)

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