10. Future Challenges
Controlling growth in subthreshold leakage currents due to lower supply voltages and, thus, lower threshold voltages
Maintaining a near constant supply voltage when delivering (on average) hundreds of amps with a variation in supply current of up to hundreds of amps
Handling power surges when large portions of chip “wake up”
Leakage currents
Decreasing supply voltage means that threshold voltages will decrease to
Help maintain signal integrity
Buy back loss in speed
But decreasing the threshold voltage means an increase in leakage current
Increase in sub-threshold current
Leakage currents increase exponentially with temperature!
Controlling leakage currents
Transistor sizing
Leakage current increases with decreasing VT and channel length while speed increases
Transistor stacking
Multiple threshold voltages
Use lower threshold devices only where speed is important
Limit leakage through dynamic control (threshold is lower when circuit is active, elevated when idle)
Substrate biasing
New technologies
SOI
Dual Threshold Voltages
Use two VT’s (e.g. 0.6V and 0.3V for Vdd = 2.5V)
Use the lower threshold for gates on the critical path
Use the higher threshold for gates off the critical path
Improves performance without an increase in power
Cons
Increased fabrication complexity
Increased design time
Beware of increased leakage in low VT portion of the circuit – could end up with increased power!
Low energy gates: transistor sizing
Use the smallest transistors that satisfy the delay constraints
Slack time – difference between required time and arrival time of a signal at a gate output
Positive slack – size down
Negative slack – size up
Make gates that toggle more frequently smaller
Size for slope engineering to reduce short circuit currents
Voltage Islands
Voltage Islands restores the concept of individual voltage optimization of functional blocks to SOC design.
One scenario involves identifying the minimum voltage required for each island to achieve its required performance.
Some functions such as embedded Analog cores, are specified at very specific voltages, and can be more easily accommodated in mixed voltage systems.
Another scenario facilitates power savings in application more sensitive standby power, such as battery powered functions.
SOC designs consist of a number of diverse functions, few of which are active at any given time.
Methods such as clock gating can be used to limit the active power from these idling functions, but the leakage power remains.
If the power supplies for these functions are partitioned into islands, the function can be completely powered off, eliminating both active and standby components of power.
Leveraging this concept requires that power management be built into the architecture and logic design of the SOC, to handling power sequencing and communications issues.
System-level Power Management Approaches
Voltage Island techniques do not replace all other methods of power management, in fact Voltage Islands concepts can complement and amplify the effectiveness of other techniques.
Clock gating can continue to be used for shorter duration “nap states” within a Voltage Island which can also be powered off for longer duration “sleep states”.
The use of multi-threshold libraries is becoming a common method for trading-off active and standby power for a function.
Design implications of Voltage Islands
Multiple power sources
Voltage Island Boundary Requirements
These methods of voltage variation present a real problem for traditional, static CMOS logic gates. When such a gate operates at a voltage sufficiently lower than the gate it drives, signal margins and performance will degrade, and the driven circuit will consume significantly higher power. Further increases in the voltage difference will eventually result in unreliable signal switching.
Additional circuitry is necessary to handle the differences in both magnitude and timing that can occur between VDD-inside and VDD-outside at island boundaries.
Circuits called Voltage Island Receivers perform this function for signals going from the parent block into the island, while Voltage Island Driver cells perform the equivalent for signals from island to parent block.
State-saving
Whereas a standard latch in a given island would operate from the island voltage (VDD-inside), a state-saving latch is a modification of the standard latch, adding both a VDD-outside connection and a state control input to select between normal and state-saving operation.
Traditional methodology for SOC architecture and chip implementation
Functional partitioning
Functional implementation
Synthesis
Design for Test (DFT) logic design and transformation
Simulation
Timing verification for entry to physical design (layout)
Floorplanning
Physical design and timing optimization
Final timing verification and release
Designing for Voltage Islands involves additional operations that affect each step in the design flow.
Methodology requirements for Voltage Island design
Functional Partitioning
Timing considerations in Synthesis and Static Timing
Design for Testability and Manufacturing Test
Logic simulation
Physical planning and implementation of Structures
An industry-wide capability to design SOC’s with voltage islands requires the following key EDA capabilities
Automatic partitioning that considers optimizing voltage levels and potential idle states of SOC functional partitions
Timing calculation and optimization capabilities that consider multiple voltages (including multiple voltage paths) and differing variations amongst multiple sources.
Consideration in DFT for multiple voltages and powering down as part of logical behavior
Verification of system functions that manage logic state during power sequencing
Automatic floorplanning and placement with constraints on proximity to power sources
Power bus automation of power supply connections, including VDD-inside/VDD-outside requirements of special circuits, and repowering of island signals requiring VDD-outside
Noise coupling analysis that considers multiple voltages and power sequencing conditions
Industry IP standards for multiple voltage functional interfaces and power, clock, and reset sequencing
TSMC 2008
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1 V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively.
Ten levels of metal stacks with different combinations of metal thickness and pitch (1X/2X and 8X) are offered to address design considerations in routing density and IR drop.
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