JNTU M TECH LOW POWER VLSI NOTES PPT

JNTU A

 M.Tech. (DSCE)                                                                                           

I Semester

LOW POWER VLSI DESIGN

(Elective I)

UNIT I

LOW POWER DESIGN, AN OVER VIEW: Introduction to low- voltage low power design, limitations, Silicon-on-Insulator.

UNIT II

MOS/BiCMOS PROCESSES: Bi-CMOS processes, Integration and Isolation considerations, Integrated Analog/Digital CMOS Process.

UNIT III

LOW-VOLTAGE/LOW POWER CMOS/ BICMOS PROCESSES: Deep submicron processes, SOI CMOS, lateral BJT on SOI, future trends and directions of CMOS/Bi-CMOS processes.

UNIT IV

DEVICE BEHAVIOR AND MODELING: Advanced MOSFET models, limitations of MOSFET models, Bipolar models. Analytical and Experimental characterization of sub-half micron MOS devices, MOSFET in a Hybrid mode environment.

UNIT V

CMOS AND Bi-CMOS LOGIC GATES: Conventional CMOS and Bi-CMOS logic gates, Performance Evaluation.

UNIT VI

LOW- VOLTAGE LOW POWER LOGIC CIRCUITS: Comparison of advanced Bi-CMOS Digital circuits. ESD-free Bi-CMOS, Digital circuit operation and comparative Evaluation.

UNIT VII

LOW POWER LATCHES AND FLIP FLOPS: Evolution of Latches and Flip flops-quality measures for latches and Flip flops, Design perspective.

UNIT VIII

SPECIAL TECHNIQUES: Power Reduction in Clock Networks, CMOS Floating Node,

Low Power Bus, Delay Balancing, Low Power Techniques for SRAM.

TEXT BOOKS:

1.   CMOS/BiCMOS ULSI low voltage, low power by Yeo Rofail/ Gohl(3 Authors)-Pearson Education Asia 1st Indian reprint,2002.

2.   Gary K. Yeap,”Practical Low Power Digital VLSI Design”, KAP, 2002.

REFERENCES:

1. Basic VLSI Design,Douglas A.Pucknell & Kamran Eshraghian,3^rd edition PHI.

2. Digital Integrated circuits, J.Rabaey PH. N.J 1996

3. CMOS Digital ICs Sung-mo Kang and yusuf leblebici 3rd edition TMH 2003 .

4.  IEEE Trans Electron Devices, IEEE J.Solid State Circuits, and other National and International Conferences and Symposia.