VHDL LAB PROGRAMS
PROCEDURE: To create, implement, simulate VHDL designs using Xilinx ISE 9.1i and ModelSim: Xilinx Edition III v6.2g.
Step 1: To start ISE, double-click the desktop icon XILINX ISE 9.1 Version.
Step 2: Start a new project by clicking File à New Project….
Step 3: In the resulting window, verify the “Top-Level Source Type” is VHDL. Change the “Project Location” to a suitable directory and give it what ever name you choose, e.g. “lab3”.
Step 4: The next window shows the details of the project and the target chip. We will be synthesizing designs into real chips so it important to match the target chip with the particular board/chip you will be using. Beginning labs will be done in a Spartan 2E XC2S200E chip that comes in a PQ208 package with a speed grade of 6 as shown.
Step 5: Since we are starting a new design the next couple of pop-up windows aren’t relevant, just click next and next and Finish.
Step 6: You should now be in the main Project Navigator window. Select Project à New Source… from the menu.
Step 7: In the resulting pop-up window specify a VHDL Module source and give the file a name. Click Next.
Step 8: The next pop-up window allows you to specify your inputs and outputs through the Wizard if you so desire. . Here, the default entity and architecture names have also been changed. Once all inputs and outputs are entered click Next and click Finish.
Step 9: Write the code in source window and once the code is completed we can proceed with a simulation of the design or we can synthesize the code for implementation and download onto an FPGA. Let us proceed with the simulation first. In the upper left-hand side of the ISE environment there is a Sources sub window which has a drop down box as shown below. Note that the drop down box currently shows “Synthesis/Implementation”.If the file name in sources window is clicked then in the process will show ‘check syntax” double click on that then errors will be displayed.and correct all the errors .
SIMULATION USING MODELSIM:
Step 1: Highlight your *.vhd file in the Sources sub window. select the “ModelSim Simulator” in the Processes sub window as shown below. Click on “Simulate Behavioral Model” to launch the ModelSim simulator.
Step 2: ModelSim should successfully launch and will open several sub windows by default. For now we just need the “Wave” and “Transcript sub windows, so close the other sub windows.
Step 3: To conduct the simulation you basically only need to know two commands, “force” and “run”. Force is used to set the value of any input variable. Then Run the simulation for a specific amount of time.Force option can be obtained by rirht click on desired variable in object window.Run option will be in in simulate option in tool bar.
AND GATE: NOR GATE
TRUTH TABLE: TRUTH TABLE:
A | B | C |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 0 |
A | B | C |
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
OR GATE: NOT GATE:
: NO
TRUTH TABLE
A | Q |
0 | 1 |
1 | 0 |
TRUTH TABLE:
A | B | C |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
NAND GATE:TRUTH TABLE
A | B | C |
0 | 0 | 1 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
1. LOGIC GATES
AIM : To simulate AND, OR, NOT, NAND, NOR,
XOR,XNOR gates Using VHDL
APPARATUS : 1.XILINX PROJECT NAVIGATOR
2. MODELSIM SIMULATOR
VHDL CODE FOR TWO INPUT AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end and2;
architecture Behavioral of and2 is
begin
z<=x and y;
end Behavioral;
VHDL CODE FOR TWO INPUT OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end or2;
architecture Behavioral of or2 is
begin
z<=a or b ;
end Behavioral;
VHDL CODE FOR TWO INPUT NAND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand2 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nand2;
architecture Behavioral of nand2 is
begin
z<=x nand y;
end Behavioral;
VHDL CODE FOR TWO INPUT NOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nor2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end or2;
architecture Behavioral of nor2 is
begin
z<=a nor b ;
end Behavioral;
VHDL CODE FOR NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in STD_LOGIC;
y : out STD_LOGIC);
end not1;
architecture Behavioral of not1 is
begin
y<=not a;
end Behavioral;
EXNOR GATE: EXOR GATE:
TRUTH TABLE: TRUTH TABLE:
A | B | Q |
0 | 0 | 1 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
A | B | Q |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 0 |
VHDL CODE FOR TWO INPUT EXCLUSIVE NOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xnor2 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xnor2;
architecture Behavioral of xnor2 is
begin
z<=x xnor y;
end Behavioral;
VHDL CODE FOR TWO INPUT EXCLUSIVE OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor2;
architecture Behavioral of xor2 is
begin
c<= a xor b;
end Behavioral;
RESULT:
DISCUSSIONS:
1.which gate is fastest gate among various logic gates?
2.which gates are said to be universal gates?
3.How many design units are there ?what are they?
4.Define entity declaration and architecture body?
2.D FLIPFLOP IC74X74
AIM : To simulate D flip-flop ic74x74 using VHDL
APPARATUS : 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM :
VHDL CODE FOR D FLIPFLOP IC74X74
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFFF is
Port ( d: in STD_LOGIC_VECTOR(0 to 1);
clk : in STD_LOGIC_VECTOR(0 to 1);
pr : in STD_LOGIC_VECTOR(0 to 1);
clr : in STD_LOGIC_VECTOR(0 to 1);
q : out STD_LOGIC_VECTOR(0 to 1);
nq :out STD_LOGIC_VECTOR(0 to 1));
end DFFF;
architecture structural of DFFF is
component dff
port(d1,clk1,pr1,clr1,:in std_logic;
q1,nq1:inout std_logic);
end component;
begin
D1:dff port map(d(0),clk(0),pr(0),clr(0),q(0),nq(0));
D2:dff port map(d(1),clk(1),pr(1),clr(1),q(1),nq(1));
end structural;
VHDL CODE FOR COMPONENT D FLIPFLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d1: in STD_LOGIC;
Clk1 : in STD_LOGIC;
Pr1 : in STD_LOGIC;
Clr1 : in STD_LOGIC;
Q1 : inout STD_LOGIC;
Nq1 :inout STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(d1,pr1,clr1,clk1)
begin
if(pr1='0' and clr1='0')then
q1<='1';nq1<='1';
elsif(pr1='0' and clr1='1')then
q1<='1';nq1<='0';
elsif(pr1='1' and clr1='0')then
q1<='0';nq1<='1';
elsif(clk1='1' and clk1'event)then
q1<=d;nq1<=not d;
end if;
end process;
end Behavioral;
RESULT:
DISCUSSIONS:
2. Explain the functions of preset and clear inputs in flip-flop?
3. What is the difference between flip-flop and latch?
4.. What are the various methods used for triggering flip-flops?
LOGIC DIAGRAM OF DECADE COUNTER
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3.DECADE COUNTER IC74X90
AIM : To simulate decade counter ic74x90 using VHDL
APPARATUS : 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM :
VHDL CODE FOR DECADE COUNTER-IC 7490
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ic7490 is
Port ( mr1 : in STD_LOGIC;
mr2 : in STD_LOGIC;
ms1 : in STD_LOGIC;
ms2 : in STD_LOGIC;
clk : in STD_LOGIC;
q : inout STD_LOGIC_vector(3 downto 0));
end ic7490;
architecture structural of ic7490 is
component jkff is
port(j,k,clk,pr,clr:in std_logic;
q,nq:inout std_logic);
end component;
signal s1,s2,s3,s4,s5,nq:std_logic;
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|
|
Begin
ff1:jkff port map('1','1',clk,s1,s2,q(0),open);
ff2:jkff port map(nq,'1',q(0),'1',s3,q(1),open);
ff3:jkff port map('1','1',q(1),'1',s4,q(2),open);
ff4:jkff port map(s5,'1',q(0),s1,s2,q(3),nq);
s1<=ms1 nand ms2;
s2<=mr1 nand mr2;
s3<=s1 and s2;
s4<=s1 and s2;
s5<=q(1) and q(2);
end structural;
VHDL CODE FOR JK FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
pr:in STD_LOGIC;
clr : in STD_LOGIC;
q : inout STD_LOGIC;
nq : inout STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
begin
process(j,k,clk,pr,clr)
begin
if(pr='0' and clr='0')then
q<=’1’;
nq<='1';
elsif(pr='0' and clr='1')then
q<='1';
nq<='0';
elsif(pr='1' and clr='0')then
q<='0';
nq<='1';
elsif(clk='0' and clk'event)then
if(j='0' and k='0')then
q<=q;
nq<=nq;
elsif(j='0' and k='1')then
q<='0';
nq<='1';
elsif(j='1' and k='0')then
q<='1';
nq<='0';
else
q<=nq;
nq<=q;
end if;
elsif(clk=’1’ and clk’event)then
q<=q;
nq<=nq;
end if;
end process;
end Behavioral;
RESULT:
DISCUSSIONS:
2.Differentiate between synchronous and asynchronous counter?
3.How many no. of flip-flops are required for decade counter?
4.What is meant by excitation table?
5.What are the meanings of different types of values in std_ulogic?
6. Write the difference between signal and variable?
PINDIAGRAM OF IC74X138
4. 3X8 DECODER IC74X138
AIM : To simulate 3x8 decoder using VHDL.
APPARATUS : 1. XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM :
VHDL CODE FOR 3 t0 8 DECODER-DATA FLOW MODEL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec3to8 is
Port ( g1 : in STD_LOGIC;
g2a_l : in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_vector(2 downto 0);
y_l : out STD_LOGIC_vector(0 to 7));
end dec3to8;
architecture dataflow of dec3to8 is
signal y_l_i:std_logic_vector(0 to 7);
begin
with a select
y_l_i<="11111110"when "000" ,
"11111101"when "001" ,
"11111011"when "010" ,
"11110111"when "011" ,
"11101111"when "100" ,
“11011111"when "101",
"10111111"when "110" ,
"01111111"when others;
y_l<=y_l_i when (g1 and (not g2a_l) and (not g2b_l))='0'
else "11111111";
end dataflow;
TRUTH TABLE:
G1 | G2A_L | G2B_L | C | B | A | Y7_L | Y6_L | Y5_L | Y4_L | Y3_L | Y2_L | Y1_L | Y0_L |
0 | X | X | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
X | 1 | X | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
X | X | 1 | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
LOGIC DIAGRAM OF 3X8 DECODER
RESULT:
DISCUSSIONS:
1. Define decoder?
2. write some of the applications where decoder is used?
3. write any four sequential statements?
4. write any four concurrent statements?
PIN DIAGRAM OF IC74X95
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TRUTH TABLE
5. FOUR_BIT SHIFT REGISTER IC74X95
AIM : To simulate 4_bit shift register ic74x95 using VHDL
APPARATUS : 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bitregister4 is
Port ( s : in STD_LOGIC;
cp1 : in STD_LOGIC;
cp2 : in STD_LOGIC;
ds : in STD_LOGIC;
d : in STD_LOGIC_vector(0 to 3);
q : inout STD_LOGIC_vector(0 to 3));
end bitregister4;
architecture Behavioral of bitregister4 is
begin
process(s,cp1,cp2,ds,d)
begin
if(s='1') then
if(cp2='0' and cp2'event) then
q<=d;
end if;
else
if(cp1='0' and cp1'event) then
q<=ds & q(0 to 2);
end if;
end if;
end process;
end Behavioral;
RESULT:
DISCUSSIONS:
2. What is a shift register?
3.Write some applications of shift register?
4.What is the function of concatenation operator?
PINDIAGRAM OF IC74X85:
6.FOUR BIT COMPARATOR
AIM : To simulate 4_bit comparator using VHDL
APPARATUS : 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity comparator is
Port(A,B:in STD_LOGIC;
ALTBIN ,AEQBIN,AGTBIN:INOUT STD_LOGIC;
AGTBOUT,AEQBOUT,ALTBOUT:INOUT STD_LOGIC);
End comparator;
Architecture comparator_b of comparator is
Begin
ALTBIN<=’0’;AEQBIN<=’1’;AGTBIN<=’0’;
Process(A,B)
Begin
If(A>B)then
ALTBOUT<=’0’;
AEQBOUT<=’0’;
AGTBOUT<=’1’;
End if;
If(A
ALTBOUT<=’1’;
AEQBOUT<=’0’;
AGTBOUT<=’0’;
End if;
If(A=B) then
ALTBOUT<=’0’;
AEQBOUT<=’1’;
AGTBOUT<=’0’;
End if;
End process;
End comparator_b;
RESULT:
DISCUSSIONS:
1.Which gate act as single bit comparator?
2.How many 4_bit comparators are required to build 16_bit comparator?
3.where do comparators are used?
4.what is the importance of package declaration?
LOGIC DIAGRAM OF 8X1 MUX:
7. IC74X151-8x1 MULTIPLEXER
AIM: Write a VHDL code for IC74151—8x1 multiplexer
APPARATUS:1.XILINX PROJECT NAVIGATOR.
2.MODELSIM SIMULATOR.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8_1 is
Port ( en : in STD_LOGIC;
d : in STD_LOGIC_vector(0 to 7);
s : in STD_LOGIC_vector(0 to 2);
y,y_l : out STD_LOGIC);
end mux8_1;
architecture Behavioral of mux8_1 is
begin
process(en,d,s)
begin
if(en='1') then
y<='0';
y_l<='1';
else
case s is
when "000"=>y<=d(0);y_l<=not d(0);
when "001"=>y<=d(1); y_l<=not d(1);
when "010"=>y<=d(2); y_l<=not d(2);
TRUTH TABLE:
when "011"=>y<=d(3); y_l<=not d(3);
when "100"=>y<=d(4); y_l<=not d(4);
when "101"=>y<=d(5); y_l<=not d(5);
when "110"=>y<=d(6); y_l<=not d(6);
when others=>y<=d(7); y_l<=not d(7);
end case;
end if;
end process;
end Behavioral;
RESULT:
DISCUSSIONS:
1. What is meant by multiplexer?
2. What does demultiplexer mean?
3. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
- Compare decoder with demultiplexer?
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