Subject : Computer Organization( CO )
Class : II B.Tech. II Sem.
Branch: ECE/ECM
UNIT - I
Multiple-Choice Questions
1. Which stores the address of the next instruction to be fetched from the main memory
to the CPU? ( ) a. PC b. MBR c. AC d. MQ
2. What is a communication pathway for connecting 2 or more devices in a computer? ( )
a. Path b. Bus c. Connection d. gate
3. Which organization has the tightly coupled systems? ( )
a. Multi processors b. Multi computers c. Multi systems d. Multi networks
4. In which organization, every CPU has its own private memory? ( )
a. Multiprocessors b. Multi computers c. Multi systems d. Multi networks
5. Which is specified by IEEE 754 standards? ( )
a. Fixed-Point Representation b. Floating-Point Representation
c. Both d. Normalization
6. What is the primary function of CPU? ( )
a. fetch b. Store c. Execute d. transfer
7. Which bus is unidirectional? ( )
a. data b. control c. address d. system
8. Which memory allows only read operation? ( )
a. RAM b.ROM c. EEPROM d. None
9. What is ISR? ( )
a. In Service Routine b. Interrupt Service Route
c. Interrupt Service Routine d. In Service Route
10. Which computer was first invented? ( )
a) E DVAC b) ENIAC c) Von Newmann d) IAS
Fill up the blanks
11. The major components of computer are _______________
12. A System software program which translates the high level language program into machine level language program is called as __________________
13. The 1’s complement of 11001010 is ______________
14. MAR stands for ______________________________
15. The pc register stores the address of _______________________
True/False Questions
16. An Error correction code is a binary code that detects digital errors during transmission. [T /F]
17. When 2 numbers of n bits are added and the sum occupies n+ 1 bit, then overflow is said to
have occurred. [T /F]
18. ALU is used only to perform Arithmetic, logic and shift operations. [T /F]
19. Parity Generator is used to detect the errors in the code. [T /F]
20. A sequence of instructions for the computer is called as program. [T /F]
UNIT - II
Multiple-Choice Questions
1. In which addressing mode, the operand is placed within the instruction? ( )
a. Absolute b. Indirect c. Immediate d. Register
2. Which of the following performs PUSH and POP Operations? ( )
a. Stack b. Queue c. Both d. Insert
3. In an instruction, which is the group of bits that specify operations to be performed such as
addition, subtraction, etc. ? ( )
a. Opcode b. Instruction Code c. Program Code d. Binary code
4. Which one of the following is a shift microoperation? ( )
a. Shift Left b. Circular Shift Left c. Arithmetic Shift Left d. All of the above
5. Which has complex and large set of instructions? ( )
a. RISC b. CISC c. DISC d. MISC
6. Which is used to describe the micro-operation transfers among Register? ( )
a. Machine level language b. Register Transfer language
c. Assembles language d. programming language
7. How many numbers of types of Instruction formats? ( )
a. 1 b. 2 c. 3 d. 4
8. In which Mode, the operands are in registers? ( )
a. Register b. Register Indirect c. Immediate d. None
9. Which of the following is the mnemonic for “load immediate”? ( )
a. LD b. LDI c. LOAD I d. LOAD
10. Which instructions transfer data between processor registers and a memory stack? ( )
a. push b. pop c. push & pop d. assembly
Fill up the blanks
11. The process of executing one instruction is called as __________________.
12. An interrupt initiated by I / O devices is called as ______________ Interrupt.
13. ________operation transfers new information to be stored into memory.
14. ________ symbol denotes transfer of information.
15. Effective Address is _________________________.
True/False Questions
16. Zero-Address Instructions operate on stack. [T /F]
17. Arithmetic instructions are part of data transfer instructions. [T /F]
18. RISC stands for Reduced Inexpensive Set Computer [T /F]
19. Placing the operator before the operand is called Reverse polish Notation. [T /F]
20. R3ßR2+ R1 +1 denote 1’s complement. [T /F]
UNIT - III
Multiple-Choice Questions
1. Which coordinates and controls the events that occur in a computer? ( )
a. Control Unit b. Arithmetic and Logic Unit c. Memory d. I/O Devices
2. In which memory, Microinstructions are stored? ( )
a. Primary Memory b. Secondary Memory c. Control Memory d. Cache Memory
3. Which address is specified by the Control memory address register? ( )
a. Instruction b. Microinstruction c. Instruction Cycle d. Micro program
4. Which implements Control Unit? ( )
a. Hardwired Control b. Microprogrammed Control
c. Nano programmed Control d. Any of the above
5. Which of the following is used for implementation of control unit makes control unit work faster?( )
a. Hardwired Control b. Microprogrammed Control
c. Nano programmed Control d. Any of the above
6. How many number of methods for implementing control unit? ( )
a. 1 b. 2 c. 3 d. None
7. Which of the following is the next address generator? ( )
a. Micro program sequencer b. program counter c. Instruction Register d. None
8. What is the name for an each group in control memory? ( )
a. Method b. tane c. Routine d. Program
9. Which rule that transforms the instruction code into a Control memory address? ( )
a. Register transfer b. Mapping c. Map d. sequence
10. Which integrated circuit implements the mapping function? ( )
a. PLA b. PLD c. ROM d. RAM
Fill up the blanks
11. __________ & ___________ are the 2 types of microinstruction organizations.
12. Fetching next microinstruction from the control memory is called as _________________.
13. A memory that is a part of control unit is called as _________________.
14. The data register is sometimes called ______________ register.
15. _____________Register is a general purpose processing register.
True/False Questions
16. A sequence of microinstructions is called as hardware. [T /F]
17. A control word is a word whose individual bits represent the various control signals. [T /F]
18. Micro programming is similar to conventional machine language programming [T /F]
19. Our computer consists of 3 memory units [T /F]
20. The most recently fetched instruction is stored in IR [T /F]
UNIT IV
Multiple-Choice Questions
1. What is the representation of (+4)10 in signed-magnitude form? ( )
a. (0100)2 b. (1100)2 c. (1011)2 d. (1111)2
2. Which performs all arithmetic and logical operations? ( )
a. ALU b. CU c. Memory d. I/O Devices
3. Which is performed by Booth’s Algorithms? ( )
a. Addition b. Subtraction c. Multiplication d. Division
4. What is 1’s complement representation of (0101)2? ( )
a. 1111 b. 1010 c. 0101 d. 0000
5. What is the representation of (-4)10 in 2’s complement form? ( )
a. (1100)2 b. (1011)2 c. (1000)2 d. (1010)2
6. How many number of ways for representing negative fixed-point binary numbers? ( )
a) 2 b) 3 c) 4 d) 1
7. Which of the following adder does the addition of two integers? ( )
a) Full b) Half c) Parallel d) None
8. Which is represented by the leftmost bit of a binary number? ( )
a) Sign bit b) One flow c) carry d) Borrow
9. How many number of digits are occupied by the sum, when two numbers of ‘n ‘digits each are added? ( )
a) n b) n + 1 c) n - 1 d) None.
10. Which uses Non Restoring method? ( )
a) Addition b) Subtraction c) Division d) Multiplication
Fill up the blanks
11. The BCD representation of (+13) 10 is ______________.
12. Addition of 2’s complement numbers (0011) 2 and (1000) 2 is ____________.
13. Subtraction of 2’s complement numbers (0011)2 and (0100)2 is _________________.
14. Booth Algorithm is used for ____________________.
15. Addition of 1’s complement number with 1 gives ______________________.
True/False Questions
16. A floating point number is said to be normalized if its most significant bit is a zero. [T /F]
17. A zero can be normalized in floating point representation. [T /F]
18. The data register is some times called as parallel registers [T /F]
19. Decimal division is similar to binary division [T /F]
20. The two magnitudes are subtracted if the signs are same [T /F]
UNIT V
Multiple-Choice Questions
1. Which is stored in memory? ( )
a. Programs b. Data c. Both a&b d. None
2. What is the time taken to access a sector in the magnetic disk? ( )
a. Seek Time b. Latency Time c. Access Time d. None
3. Which memory allows data to be written only once into it? ( )
a. Cache b. RAM c. ROM d. MagneticDisk
4. Which RAM needs periodical refresh, to store data for a long time? ( )
a. Static b. Dynamic c. Both a & b d. None
5. Which is related with the “Locality of Reference”? ( )
a. Cache Memory b. Main Memory c. Magnetic Disk d. ROM
6. What memory is accessed by its content? ( )
a. cache memory b. virtual memory c. associative memory d. auxiliary memory
7. Which is a non volatile memory? ( )
a. RAM b. SRAM c. DRAM d. ROM
8. When the addressed word in a read operation is not in the cache, then which is occurred?( )
a. write miss b. read miss c. read hit d. write hit
9. What stands for LRU? ( )
a. least recently used b. last recently used
c. long recently used d. both c&d
10. What is the time required to move the read/write head to the proper track? ( )
a. Latency Time b. Seek Time c. Access Time d. propagation time
Fill up the blanks
11. Hit ratio means _________________________.
12.________________ is one of the mapping techniques for cache memory.
13. When a program generates an access request to the page that is not available in the main memory, then a ____________ is said to have occurred.
14. The electronic circuitry that controls the operation of the system is called------------
15. Mapping techniques are ____________________, __________________, _________________.
True/False Questions
16. The number of hits to the total number of memory accesses is called as hit rate. [T /F]
17. Main Memory is a Secondary Storage. [T /F]
18. RAM s are volatile memories [T /F]
19. The number of words in the block to be referred as word count [T /F]
20. Data on the tape are organized in the form of records separated by gaps. [T /F]
UNIT VI
Multiple-Choice Questions
1. Which of the following is one of the modes of transfer? ( )
a. Programmed I/O b. Interrupt-Driven I/O c. DMA d. All of the above
2. In which, DMA controller transfers one data word at a time and transfers the control of the bus to CPU? ( )
a. Burst Transfer b. Daisy Chaining c. Cycle Stealing d. Polling
3. Which of the following uses different address space for memory and I/O? ( )
a. Independent I/O b. Isolated I/O c. Memory-mapped I/O d. Interrupt-Driven I/O
4. What is the rate at which serial information is transmitted and is equivalent to the data transfer rate in bits/sec? ( )
a. Baud Rate b. Bit Rate c. Control Rate d. Strobe Rate
5. In which asynchronous data transfer, both sender and receiver accompany a control signal?( )
a. Strobe b. Handshaking c. Two-wire control d. Single-wire control
6. Which of the following is Input or Output device attached to the computer? ( )
a.) monitor b.) keyboard c.) printer d.) peripheral
7. What is ASCII? ( )
a.) American Standard Code for International Interchange
b) American Standard Code for Interchange Information
c) American Standard Code for Information Interchange
d) American Standard Code for International Information.
8. How many number of printed characters and non printed characters used for various control statements in the ASCII code? ( )
a) 94 & 34 b) 34 & 94 c) 24 & 84 d) 84 & 24
9. In between which devices, Input-output interface provides a method for transferring information?( )
a) Internal I/O and External Storage b) Internal Storage and External I/O c) both a & b d) none
10. Which command causes the interface to respond by transferring data from the bus into one of its registers? ( )
a.) I/O command b.) control command c.) status command d.) output data command
Fill up the blanks
11. DMA stands for _____________
12. ______ is one of the protocols for serial communication.
13. A processor with DMA capability that communicates with I/O devices is _________ processor.
14. _________ command is the opposite of the data output.
15. The I/O interface consists of two data registers called ______________.
True/False Questions
16. Programmed I/O mode of transfer is more efficient among all the techniques. [T /F]
17. Magnetic Disk is a Peripheral Device. [T /F]
18. The memory read and memory write control lines are enabled during memory transfer [T /F]
19. The strobe pulse supplied by one of the units to indicate to the other unit when the transfer has occurred [T /F]
20. The strobe pulse method and the handshaking method of asynchronous data transfer are restricted to I/O transfers. [T /F]
UNIT VII
Multiple-Choice Questions
1. How many number of stages Instruction pipelining? ( )
a. 2 b. 3 c. 4 d. 6
2. Which pipeline divides arithmetic operations into sub-operations to speedup the operation?( )
a. Arithmetic b. Instruction c. Shift d. Subtract
3. Which technique may be used for handling branch instructions in an instruction Pipeline? ( )
a. Prefetch target b. Loop Buffer c. Branch Prediction d. Any of the above
4. Which Conflicts arise, when an instruction depends on the result of a previous instruction?( )
a. Resource b. Branch c. Segment d. Data Dependency
5. Which of the following organization is in an SIMD array processor? ( )
a. Single instruction, Single data b. Single instruction, Multiple data
c. Multiple instruction, Single data d. Multiple instruction, Multiple data
6. Which represents the organization of a single computer containing a control unit, a processor unit, and a memory unit? ( )
a) SISD b.) SIMD c.) MISD d.) MIMD
7. Which techniques are denoted by the term Parallel processing that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer? ( )
a) small class b) middle class c)medium class d)large class
8. Which diagram is used to illustrate the behavior of a pipeline? ( )
a) linear time diagram b)nonlinear time diagram c)space time diagram d)array time diagram
9. Which are caused by access to memory by two segments at the same time? ( )
a) data conflicts b) resource conflicts c) source conflicts d)destination conflicts
10. Which is used to refer the concept of delaying the use of the data loaded from memory? ( )
a) Delayed branch b) delayed load c) delayed time d) all the above
Fill up the blanks
11. In __________ systems, concurrent data processing is performed to achieve faster execution.
12. ____________ Method can be used to handle data dependency conflicts.
13. A measure used to evaluate computers in their ability to perform a given number of floating-point operations/sec is ______________.
14. An attached array processor is an ___________ processor attached to a general-purpose computer.
15. MIMD stands for____________________.
True/False Questions
16. Data dependency conflict increases the efficiency of pipeline. [T /F]
17. Vector processing deals with computations involving large matrices. [T /F]
18. SIMD represents an organization that includes many processing units under the supervision of a common control unit. [T /F]
19. Flynn’s classification depends on the distinction between the performance of the memory unit and the data-processing unit [T /F]
20. K-segment pipeline with a clock cycle time tp is used to execute n tasks. [T /F]
UNIT VIII
Multiple-Choice Questions
1. Which is the system that does not have parallel processing capabilities? ( )
a. SISD b. SIMD c. MISD d. MIMD
2. What controller monitors the cache coherence problem? ( )
a. Snoopy Cache controller b. Split cache controller
c. Direct cache controller d. Side cache controller
3. In which multiprocessor system, memory is distributed among the processors and there is no shared memory? ( )
a. Tightly coupled b. Shared memory
c. Loosely Coupled d. Specialized
4. Which is the common communication mechanism used between the processors? ( )
a. FIFO b. Semaphore c. Shared Memory d. Message Queue
5. Which interconnection is suitable for connecting small number of processors? ( )
a. Crossbar switch b. Connection Point c. Switch d. Hub
6. Which of the following is Multiprocessor? ( )
a. SISD b. SIMD c. MISD d. MIMD
7. Which is formed by the computers those are interconnected with each other by means of communication lines? ( )
a) communication b) computer c) Local Area d) Wide area
8. Which can improve performance by decomposing a program into parallel executable tasks? ( )
a.) serialize executable b.) random executable c.) Multiprocessing d.) both a & b
9. Which is a multiprocessor system with common shared memory? ( )
a.) shared memory or tightly coupled multiprocessor
b.) distributed memory or loosely coupled
c.) shared memory or loosely coupled
d.) Distributed memory or tightly coupled multiprocessor
10. Which memory system employs separate buses between each memory module and each CPU?( )
a.) single port b.) multi port c.) multiple d.) none
Fill up the blanks
11. In serial arbitration procedure, the device closest to the priority line is assigned __________ priority.
12. ____________ must be performed to resolve multiple contentions for shared resources
13. In ______________ bus, each data item is transferred during a time slice known to source and destination in advance.
14. The ________ switch organization consists of a number of crosspoints that are placed at intersections between processor buses and memory module paths.
15. The basic component of a multistage network is a _______ interchange switch.
True/False Questions
16. In write-back mechanism both cache and main memory are updated with every write operation.
[T /F]
17. In Multi port multiprocessor system, the number of processors is connected through a common path to a memory unit. [T /F]
18. The two processors P1 and P2 are connected through switches to eight memory modules marked in binary from 000 through 111. [T /F]
19. In Multistage Switching Network the first bit of the destination number determines the switch input in the first level [T /F]
20. The hypercube or binary n-cube multiprocessor structure is a tightly coupled system. [T /F]
ANSWERS:
| QUE. NO. | UNIT I | UNIT II | UNIT III | UNIT IV | UNIT V | UNIT VI | UNIT VII | UNIT VIII |
| 1 | A | C | A | A | C | D | A | A |
| 2 | B | A | C | A | B | C | A | A |
| 3 | A | A | B | C | C | C | A | C |
| 4 | B | D | D | B | B | A | D | C |
| 5 | B | B | A | A | A | B | B | A |
| 6 | A | B | B | B | C | D | A | D |
| 7 | C | C | A | C | D | C | D | B |
| 8 | B | A | C | A | B | A | C | C |
| 9 | C | A | B | B | A | B | B | A |
| 10 | B | C | B | C | B | D | B | B |
| 11 | CPU, IO devices, Memory | Instruction Cycle | Horizontal & Vertical | 0001 0011 | No. of hits /( No. of hits + No. of Misses) | Direct Memory Access | Parallel | Highest |
| 12 | Compiler | External | Micro instruction Sequence | 1011 | Associative Mapping / Direct Mapping / Set-Associative Mapping | Character- Oriented Protocol / Bit – Oriented Protocol | Hardware Interlocks/ Operand Forwarding/ Delayed load | Arbitration |
| 13 | 00110101 | Write | Control memory | 1111 | Page fault | I / O | FLOPS | Synchronous |
| 14 | Memory Address Register | <------ | Pipeline | Multiplication | Disk controller | Data input | Auxiliary | Cross bar |
| 15 | Next instruction | Address of an operand | Accumulator | 2’s complement | Associative, Direct, Set-Associative Mapping | Ports | Multiple Instruction, Multiple Data | 2 input, 2 output |
| 16 | F | T | F | F | T | F | F | F |
| 17 | T | F | T | F | F | T | T | T |
| 18 | F | F | T | F | T | T | T | T |
| 19 | T | F | F | F | T | T | F | F |
| 20 | T | F | T | F | T | F | T | F |
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